Semiconductor transistors, in particular field-effect controlled switching devices such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor), in the following also referred to as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a HEMT (high-electron-mobility Field Effect Transistor) also known as heterostructure FET (HFET) and modulation-doped FET (MODFET) are used in a variety of applications. An HEMT is a transistor with a junction between two materials having different band gaps, such as GaN and AlGaN.
HEMTs are viewed as an attractive candidate for power transistor applications, i.e., applications in which switching of substantially large voltages and/or currents is required. HEMTs offer high conduction and low resistive losses in comparison to conventional silicon based devices.
HEMTs are commonly formed from III-V semiconductor materials, such as GaN, GaAs, InGaN, AlGaN, etc. In a GaN/AlGaN based HEMT, a two-dimensional electron gas (2DEG) arises at the interface between the AlGaN barrier layer and the GaN buffer layer. The 2DEG forms the channel of the device instead of a doped region, which forms the channel in a conventional MOSFET device. Similar principles may be utilized to select buffer and barrier layers that form a two-dimensional hole gas (2DHG) as the channel of the device. A 2DEG or a 2DHG is generally referred to as a two-dimensional carrier gas. Without further measures, the heterojunction configuration leads to a self-conducting, i.e., normally-on, transistor. Measures must be taken to prevent the channel region of an HEMT from being in a conductive state in the absence of a positive gate voltage.
One technique for forming the type III-V semiconductors used in HEMTs involves using a using a silicon wafer as a base substrate and epitaxially growing type III-V semiconductor material on the silicon wafer base substrate. Silicon wafers are widely available within the industry and thus provide a cost-effective platform for epitaxially growing type III-V semiconductor material.
One issue related to III-V semiconductor epitaxial formation relates to wafer bowing. Wafer bowing refers to a convex or concave shaped warpage of the completed device. That is, an upper surface of the device is curved instead of planar. One source of wafer bow relates to the processes and materials used to form the III-V semiconductor layers. Typically, type III-V semiconductor layers are formed on a silicon base wafer using a high temperature (e.g., 600° C. to 1000° C.) epitaxial deposition process. The epitaxial deposition is followed by a cooling cycle. These thermal cycles cause the materials to expand and contract. This expansion and contraction can be problematic, particularly when materials having different coefficients of thermal expansion are used. An example of this is the above described device in which the silicon substrate has a different coefficient of thermal expansion as the III-V semiconductor layers that are formed on the silicon substrate. As the device cools, mechanical stress (e.g., compressive stress and tensile stress) arises in the device, which causes the device to bow. This bowing can cause cracks to propagate in the finalized device. This issue can harm device performance and/or detrimentally impact yield.